1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing thereof.
2. Description of the Related Art
A memory cell composing DRAM generally consists of a transistor for memory cell and a capacitive element. Capacitor over bit line (COB) DRAM having a structure, in which a capacitive element of DRAM is disposed over a bit line, is proposed for achieving higher degree of integration of the memory cell. Typical conventional structure of such COB DRAM is shown in FIG. 13.
In this type of the conventional DRAM, a MOS transistor formed on a semiconductor substrate such as a silicon substrate 10 or the like functions as a transistor for memory cell. A bit line 6 is formed on an upper layer of the transistor for a memory cell through a cell-contact interlayer film 8, and a capacitive element 11 is formed on an upper layer of the bit line 6 through a capacitive-contact interlayer film 7. The bit line 6 is coupled to a transistor for memory cell formed on the silicon substrate 10 by being coupled to a cell contact 9 through a barrier metal layer 5, and the capacitive element 11 is coupled to the transistor for memory cell formed on the silicon substrate 10 through the capacitive contact 4 and the cell contact 9.
Although FIG. 13 illustrates the barrier metal layer 5 provided as an underlying layer disposed under the bit line 6, it is intended to additionally include the barrier metal layer 5 when the term “bit line 6” appears in the following description.
In such structure, it is designed to include a configuration of maintaining a predetermined spacing between the bit line 6 and the capacitive contact 4 or the cell contact 9, in order to inhibit a generation of electric short circuit. However, since the progresses in increasing the level of the integration in the semiconductor devices necessarily reduce the room for the spacing between the bit line 6 and the capacitive contact 4 or the cell contact 9, a short circuit may be occurred between the bit line 6 and the capacitive contact 4 or the cell contact 9 by a misalignment caused in the formation of the bit line 6 or a misalignment caused in the formation of the capacitive contact 4 or the like. When the short circuit is occurred between the bit line 6 and the capacitive contact 4 or the cell contact 9 as described above, failure easily occurs in the resultant memory cell, thereby occasionally reducing the yield of DRAM.
Further, FIG. 13 also illustrates that diameters of the capacitive contact 4 and the cell contact 9 are constant at both the upper and the lower ends. However, as shown in FIG. 14, the reality is that the diameters of the capacitive contact 4 and the cell contact 9 at the upper ends thereof is larger than those at the lower ends, thereby forming the inverse tapered shapes. Therefore, the room for the spacing for preventing the short circuit between the bit line 6 and the cell contact 9 becomes smaller than the room for the spacing for preventing the short circuit between the bit line 6 and the capacitive contact 4.
Thus, a semiconductor device additionally including a bit contact interlayer film 13 formed on the cell contact interlayer film 8 is proposed, for the purpose of inhibiting the short circuit between the bit line 6 and the cell contact 9. The constitution of such conventional semiconductor device is shown in FIG. 15. In this type of conventional semiconductor device, a bit contact interlayer film 13 is formed after forming the cell contact interlayer film 8, and a bit contact 14 is formed on a portion of the bit contact interlayer film 13 that provides coupling of the cell contact 9 to the bit line 6. Having such structure, larger room for the spacing for preventing the short circuit between the upper end of the cell contact 9 and the bit line 6 can be acquired by extending the distance therebetween.
Next, a method for manufacturing a semiconductor device having a structure, in which a bit contact interlayer film 13 is formed to extend the room for the spacing for preventing the short circuit at the upper ends of the bit line 6 and the cell contact 9, will be described as follows with reference to FIG. 16 to FIG. 23.
First of all, as shown in FIG. 16, shallow grooves are formed on a silicon substrate 10, similarly as in the typical manufacturing process for DRAM, and the grooves are filled with an insulating material to form element isolation insulating films 3, so that the memory cell area is sectioned into individual cell areas. Then, an impurity is implanted into the silicon substrate 10 to form source drain regions 2, thereby forming MOS transistors, which will be transistors for the memory cells.
Next, cobalt silicide layers 12 are formed by silicidating the entire surfaces of the diffusion layers and the gates of respective transistors with cobalt. Thereafter, silicon nitride films 1 are formed on the surface of the silicon substrate 10 containing the surfaces of element isolation insulating films 3 to coat the respective transistors.
Next, cell contact interlayer films 8 are formed by using a material such as silicon oxide or the like so as to cover the respective transistors for memory cells in the memory cell area. Then, contact holes for coupling the bit line and the capacitive element to transistors for memory cells in the cell contact interlayer films 8 are formed via a selective etch process. Then, tungsten (W) is deposited on the entire surfaces thereof via a chemical vapor deposition (CVD) until the contact holes are filled therewith, after depositing the barrier metal layer of titanium nitride (TiN) in the contact hole. Thereafter, the surfaces of the cell contact interlayer films 8 are planarized via a chemical mechanical polishing (CMP) so as to leave W only in respective contact holes, thereby forming cell contacts 9. A cross sectional view of the semiconductor device after the steps so far are finished is shown in FIG. 16.
Next, as shown in FIG. 17, a bit contact interlayer film 13 comprising silicon oxide is formed to a predetermined thickness on the surfaces of the cell contact interlayer films 8 that include exposed surfaces of the cell contact 9 to coat the surfaces of the cell contacts 9 therewith. Then, the bit contact interlayer film 13 is etched so that only the positions directly above the portions electrically coupled to the bit lines 6 are selectively etched among the cell contacts 9 to form contact holes, thereby exposing the upper surface of the cell contacts 9. Then, W is deposited via CVD until the formed contact holes are filled therewith after depositing the barrier metal layer of titanium nitride (TiN) in the contact hole, similarly as in the formation process of the cell contacts 9, and the surfaces thereof are planarized via CMP so as to leave W only in respective contact holes, thereby forming bit contacts 14 for coupling to the bit lines 6. A cross sectional view of the semiconductor device after the steps so far are finished is shown in FIG. 17.
Next, as shown in FIG. 18, titanium nitride (TiN) film 19 for forming barrier metal layers 5 and tungsten (W) film 20 for forming bit lines 6 are deposited on the surfaces of the bit contact interlayer film 13.
Then, as shown in FIG. 19, photo resists 18 are formed on the portions on the tungsten film 20, on which bit lines are formed. Then, as shown in FIG. 20, these layers are patterned to form bit lines 6 and barrier metal layers 5 having predetermined geometries through the mask of the photo resist 18. The photo resists 18 are then stripped after the bit lines 6 and the barrier metal layers 5 are formed. A cross sectional view of the semiconductor device after the steps so far are finished is shown in FIG. 21.
Then, similarly as in the formation process for the cell contacts 9 or the bit contacts 14, W is deposited via CVD until the contact holes are filled therewith after depositing the barrier metal layer of titanium nitride (TiN) in the contact hole, and the surfaces thereof are planarized via CMP so as to leave W only in respective contact holes, thereby forming capacitive contacts 4 for coupling to the capacitive elements 11. A cross sectional view of the semiconductor device after the steps so far are finished is shown in FIG. 22.
Then, a capacitive element 11 for coupling to the capacitive contact 4 is finally formed to complete the semiconductor device. A cross sectional view of the semiconductor device after the steps so far are finished is shown in FIG. 23.
In such conventional semiconductor device, a bit contact interlayer film 13 is provided to keep the bit line 6 and the cell contact 9 apart from each other, thereby ensuring the room for the spacing for preventing the short circuit. However, since the conventional semiconductor device having such constitution requires additionally forming the bit contact interlayer film 13 and the bit contact 14, the number of the processing steps may be considerably increased.
Further, the contact resistance thereof may be increased due to the existence of the bit contact 14 therebetween, as compared with the case where the bit line 6 is formed directly on the cell contact interlayer film 8.
A typical conventional method for manufacturing a semiconductor device having a constitution of preventing the short circuit of the bit line and the cell contact may be a method disclosed in, for example, JP-A-2001-257,325. In such conventional method for manufacturing the semiconductor device, where the bit contact interlayer film is not used, polycrystalline silicon is deposited in the interior of the contact hole to a level lower than the upper surface of the interlayer insulating film, and thereafter a silicide film is formed on the upper part of the polycrystalline silicon, in order to prevent a short circuit between the contact for the capacitive coupling and the bit line. Then, the side wall is formed after the formation of the bit line, and thereafter, the silicide film formed within the contact hole interior that is not covered with bit line is removed, thereby broadening the distance between the contact and the bit line.
Although the room for the spacing for preventing the short circuit between the bit line and the contact can be maintained without providing the bit contact interlayer film according to such conventional method for manufacturing the semiconductor device, the method requires additional processes such as a process for forming a side wall after the bit line formation, a process for forming a silicide film on the upper part of polycrystalline silicon in the contact hole, a process for removing the silicide film after bit line formation or the like, and thus the number of the processing steps is considerably increased.
The conventional method for manufacturing the semiconductor device stated above has a configuration, in which a room for the spacing for preventing the short circuit between the bit line and the cell contact is ensured by comprising the bit contact interlayer film, and therefore it is difficult to stably provide semiconductor devices having higher reliability.